Motivation


The motivation for this webpage is to share my work on:

    - PDVL: An aspect and transaction oriented Programming, Design and Verification Language,

    - SHP: System Hyper Pipelining,

    - as well as ASIC testing related projects (DFT).

News:


2020/Mar/05: Latest ACM paper on "Combining Simulation and FPGA Based Verification to an Affordable and Ultra-Fast Multi-Billion-Gate Verification System" is now online: here.


2019/Dec/20: RISC-V based Arduissimo project released.


2019/Aug/1: I will give a talk on "Combining Simulation and FPGA Based Verification to an Afforfable and Ultra-Fast Multi-Billion-Gate Verification System" at the Rapid System Prototyping Workshop in October 2019, New York, USA.



2019/June/16: I will give a talk on "An RTL ATPG Flow Using the Gate Inherent Fault (GIF) Model Applied on Non-, Standard- And Random-Access-Scan (RAS)" 
at the Euromicro DSD conference in August 2019, Kallithea, Greece.


2018/July/18: Latest IEEE paper on PDVL and "Dynamic Inside-Out Verification Using Inverse Transactions in TLM" is now online: https://ieeexplore.ieee.org/document/8524048.


2018/May/9: I will give a talk on PDVL and "Dynamic Inside-Out Verification Using Inverse Transactions in TLM" at the FDL-conference in Munich, http://www.fdl-conference.org.



last modified: 2020/Mar/5