|
Publications:
[20] T.
Strauch, "Non-interfering On-line and In-field
Testing", 35th Workshop on Rapid System Prototyping, 3rd Oct. 2024,
Raleigh, NC, USA, pp. 1-7
[19] T.
Strauch, "Transaction Level Hierarchy Guided and
Functional Coverage Driven Deductive Formal Verification", 35th
Workshop
on Rapid System Prototyping, 3rd Oct. 2024, Raleigh, NC, USA, pp. 1-7
[18] T.
Strauch, “Deductive Formal Verification of Synthesizable,
Transaction-level Hardware Designs Using Coq”, 2024 Design,
Automation &
Test in Europe Conference & Exhibition (DATE), 25-27 March
2024, Valencia,
Spain, pp. 1-7
[17] T.
Strauch, “MRPHS: A Verilog RTL to C++ Model Compiler using
Intermediate Representations for Object-oriented Model-driven
Prototyping”,
34th Workshop on Rapid System Prototyping, 21st Sep. 2024, Hamburg,
Germany,
pp. 1-7
[16] T.
Strauch, „Combining
Simulation and FPGA Based Verification to an Affordable and Ultra-Fast
Multi-Billion- Gate Verification
System“, 30th
Intern. Workshop on Rapid System Prototyping,
17-18 Oct. 2019, New York, USA
[15] T.
Strauch, „An RTL ATPG
Flow Using the Gate Inherent Fault (GIF) Model Applied on Non-,
Standard- and Random-Access-Scan (RAS)“,
IEEE Euromicro DSD 2019, 28-30 Aug.
2019,
Kallithea, Greece, pp. 51-60
[14] T.
Strauch, „Dynamic
Inside-Out Verification Using Inverse Transactions in TLM“,
Forum on Specification
& Design Languages
2018, FDL, 10 – 12 Sept. 2018, Garching, Germany
[13] T.
Strauch, „Connecting
Things to the IoT by Using Virtual Peripherals on a Dynamic Multithreaded
Cortex M3“, IEEE
Transactions on Circuits and Systems I: Regular Papers, vol.
64, issue 9, Sep. 2017, pp. 2462 - 2469
[12] T.
Strauch,
„Acceleration Techniques for System-Hyper-Pipelined
Soft-Processors on FPGAs“,
IEEE Euromicro DSD 2017, 30 Aug. -
1 Sep., Vienna, Austria, pp. 129 - 138
[11] T.
Strauch, „An Aspect
and Transaction Oriented Programming, Design and Verification Language“,
IEEE Euromicro DSD 2017, 30 Aug. -
1 Sep., Vienna, Austria, pp. 30 - 39
[10] T.
Strauch, „A Novel RTL
ATPG Model Based on Gate Inherent Faults of Complex
Gates“, 20th
Workshop
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von
Schaltungen und Systemen, MBMV
2017, 8 - 9 Feb., Bremen, Germany, pp. 117 - 128
[9]
T.
Strauch, "A
Many-Core Solution for the Multi-Objective Challenge in the Field
of Dynamic
Cycle Accurate
Verification", ARCS 26, 29th International Conference
on Architecture
of Computing
Systems, 4-7 April 2016, Nuremberg, Germany, pp. 1-8.
[8] T.
Strauch, "Using
System Hyper Pipelining (SHP) to Improve the Performance of a Coarse-Grained
Reconfigurable Architecture
(CGRA) Mapped on an FPGA", 2nd International Workshop
on FPGAs for Software Programmers, FSP 2015, 1 Sep.,
London, UK, pp. 1 - 6
[7] T.
Strauch, "The
Effects of System Hyper Pipelining on Three Computational
Benchmarks Using
FPGAs", 11th
International Symposium in Applied Reconfigurable Computing, ARC 2015,
13-17 April 2015, Bochum, Germany,
pp. 1 - 12
[6] T.
Strauch,
"Deriving AOC C-Models from D&V Languages for Single- or
Multi-Threaded Execution
using
C or C++", 18. Workshop Methoden und
Beschreibungssprachen
zur Modellierung
und
Verifikation von Schaltungen und Systemen, MBMV 2015, 3-4
March, Chemnitz,
Germany, pp. 1 - 12
[5] T.Strauch,
"Using
C-Slow Retiming in Safety Critical and Low Power Applications", First International
Workshop on FPGAs in
Aerospace Applications", FASA 2014, 5 September 2014,
Munich, Germany
[4]
T.Strauch,
"Timing Driven C-Slow Retiming on RTL for MultiCores on FPGAs", ParaFPGA2013,
10-13 September 2013, Munich,
Germany, IOS Press 2014 Advances in Parallel
Computing ISBN
978-1-61499-380-3, pp. 512 – 522
[3] T.Strauch,
"Timing Driven
RTL-to-RTL Partitioner for Multi-FPGA Systems", 23rd International
Conference on Field
Programmable Logic and Applications, 2-4 September 2013,
Porto, Portugal, pages 1-4
[2] T.
Strauch, "Single Cycle
Access Structure for Logic Test", IEEE Trans. on VLSI, vol. 20,
no.
5, May 2012, pp. 878 – 891
[1] T.
Strauch, "Multi-FPGA
System With Unlimited and Self-Timed Wave-Pipelined Multiplexed
Routing", IEEE Trans. on VLSI, vol. 19.
no. 9, Sep. 2011, pp.1549 - 1558
| last
modified: 2025/April/5 |
|
|